NAND flash memory devices have a command/address/data multiplexing input/output port structure in a known manner. The NAND flash memory device with the multiplexing input/output port structure adopts command and address preset manners. The command preset manner is to preset an operation to be performed after inputting predetermined data combination (for example, “00h”, “60h”, “70h”, “80h”, “FFh”, and the like) in a memory device via input/output pins. The address preset manner is to preset an address needed for writing/reading out data into/from a memory device. Unlike a semiconductor memory device such as a static random access memory (SRAM) device, the NAND flash memory device performs a read/write operation after presetting a command and an address. In the case of the NAND flash memory device, it is possible to share address input pins and data input/output pins. This is because an input interval of data is completely separated from an input interval of an address or a command.
A 64 M×8 bit NAND flash memory device, for example, includes 8 input/output pins I/00–I/07 and 5 control pins CLE, ALE, /WE, /RE, and /CE. As explained above, the 8 input/output pins are used when an address and a command are inputted and when data is inputted and outputted. A signal applied to the control pin CLE is a command latch enable signal informing that data inputted via input/output pins is a command, and a signal applied to the control pin ALE is an address latch enable signal informing that data inputted via input/output pins is an address. A signal applied to the control pin /WE is a write enable signal that is an input clock or synchronous signal of an address, a command, and data, and a signal applied to the control pin /RE is a read enable signal that is an output clock or synchronous signal of data. A signal applied to the control pin /CE is a chip enable signal. In the case of a 512 M-bit NAND flash memory device, a 26-bit address is required and four-cycle toggling of the write enable signal /WE is needed to receive the 26-bit address via 8 input/output pins. Because the number of the input/output pins of the foregoing memory device is 8, the number of data lines for internally transferring data is also 8. That is, a typical NAND flash memory device has the same data interface structure as an address/command interface structure.